Title:
TRANSIMPEDANCE AMPLIFIER
Document Type and Number:
WIPO Patent Application WO/2020/090519
Kind Code:
A1
Abstract:
On different wiring layers S1 and S2 of a substrate 1, a negative feedback inductor Lc and a gate inductor Lb are formed so as to at least partially overlap with each other in a plan view. When the wiring layer S1 which is a lower layer has a small thickness and the wiring layer S2 which is an upper layer has a large thickness, the negative feedback inductor Lc is formed on the wiring layer S1 which is the lower layer with small thickness. This makes it possible to achieve saving the area.
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Inventors:
TANAKA KENJI (JP)
MIURA NAOKI (JP)
FUKUYAMA HIROYUKI (JP)
NOSAKA HIDEYUKI (JP)
MIURA NAOKI (JP)
FUKUYAMA HIROYUKI (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2019/041059
Publication Date:
May 07, 2020
Filing Date:
October 18, 2019
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03F1/34; H03F3/70; H03F1/42; H03F3/195
Domestic Patent References:
| WO2012036207A1 | 2012-03-22 |
Foreign References:
| JP2015154485A | 2015-08-24 | |||
| JP2013529435A | 2013-07-18 | |||
| JPH0214605A | 1990-01-18 | |||
| JP2013522955A | 2013-06-13 | |||
| JP2015019105A | 2015-01-29 |
Other References:
GHASEMI OMIDREZA: "Combination of Inductive Feedback and Shunt Peaking (IF+SHP) for Bandwidth Extension of Transimpedance Amplifiers", 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 6 December 2015 (2015-12-06), pages 145 - 148, XP032884801, DOI: 10.1109/ICECS.2015.7440270
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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