Title:
WORD LINE DRIVE CIRCUIT AND DYNAMIC RANDOM ACCESS MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/083137
Kind Code:
A1
Abstract:
A word line (WL) drive circuit and a dynamic random access memory. The WL drive circuit comprises a first transistor (N1), a second transistor (N2), a third transistor (N3), and a fourth transistor (P1). A gate of the first transistor (N1) is connected to a WL opening voltage (bMWL), and a drain of the first transistor (N1) is connected to a WL. A gate of the second transistor (N2) is connected to a first drive voltage (PXIB) of the WL, and a drain of the second transistor (N2) is connected to the WL. A source of the first transistor (N1) and a source of the second transistor (N2) are both connected to a negative bias voltage (VSS) by means of the third transistor (N3). The source of the first transistor (N1) and the source of the second transistor (N2) are not directly connected to the negative bias voltage (VSS), but are connected to the negative bias voltage (VSS) by means of the third transistor (N3). In this way, when the WL drive circuit is in an active mode, the leakage current generated by the first transistor (N1) and the second transistor (N2) can be effectively reduced, thereby reducing the power consumption of the dynamic random access memory.
Inventors:
YANG CHENG-JER (CN)
Application Number:
PCT/CN2021/099504
Publication Date:
April 28, 2022
Filing Date:
June 10, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/408; G11C8/08
Foreign References:
| KR20110059124A | 2011-06-02 | |||
| CN1799103A | 2006-07-05 | |||
| CN104050999A | 2014-09-17 | |||
| CN110148433A | 2019-08-20 | |||
| US20150255146A1 | 2015-09-10 | |||
| US20170178751A1 | 2017-06-22 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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