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JP3020517B2 |
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JP3019155B2 |
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JP3011965B2 |
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JP3004701B2 |
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JP2000032073A |
To improve the multi-bus performance and to maintain the orthogonality of a Walsh code and also the low mutual relation characteristic of Walsh codes by deforming an orthogonal Walsh code by means of plural codes and improving the self-c...
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JP2998899B2 |
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JP2998898B2 |
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JP2994941B2 |
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JPH11345033A |
To make it possible to execute high speed and stable control even in the case of using an inexpensive microcontroller by setting up a timer/counter value indicating the time until interruption is generated in a main process and after the...
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JP2990698B2 |
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JPH11330932A |
To obtain a pulse-width modulation output having narrow pulse width. First and second triangular wave generating circuits 100 and 200 generate triangular waves TRI1 and TRI2 which are different 180° in the phase with each other and have...
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JP2978270B2 |
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JP2978271B2 |
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JP2976452B2 |
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JP2976610B2 |
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JP2973434B2 |
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JP2967577B2 |
A pulse width modulation (PWM) circuit is disclosed for multiple channels. The circuit allows output pulses of a PWM signal for each channel to be distributed not simultaneously but with a time difference so that the power consumption is...
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JP2960744B2 |
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JP2960745B2 |
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JP2958962B2 |
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JP2955038B2 |
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JP2957493B2 |
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JP2955117B2 |
PURPOSE: To reduce the size of a buffer and to decrease a current consumption. CONSTITUTION: A data latch circuit latches H period setting data and L period setting data given from a pulse width control means and varied respectively inde...
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JP2949349B2 |
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JPH11243340A |
To prevent distortion from occurring in an output analog single and to quickly respond to the level change of an input digital signal with respect to a digital signal input around a center level. This converter contains a 4-bit counter 2...
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JP2946534B2 |
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JP2940825B2 |
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JPH11225471A |
To reduce malfunctions due to noise. An analog signal is once converted into a digital signal before being input to an error amplifier 6. More specifically, in front of a positive input to an error amplifier 6, an A/D converter 8, a resi...
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JP2929567B2 |
PURPOSE: To obtain a calculation cycle in a switching time without increasing calculation costs in a digital modulation method for modulating a constant input signal (e)k in each period in a series of individual time intervals Δtk into ...
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JPH11205105A |
To improve the control accuracy of a pulse width to be outputted. A counter 1 up-counts clock pulses CLK and a lower limit value setting circuit 2 and an upper limit value setting circuit 3 respectively output a lower limit value S1 and ...
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JP2924601B2 |
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JPH11196579A |
To reduce the production of a minimum pulse width (or off-width between pulses) in a low output power (or high output power) operation as possible and realize excellent control characteristics. The amplitude of a signal wave is calculate...
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JP2912290B2 |
In a pulse width modulation (PWM) control circuit, a free run counter counts a clock signal to count a time value, and generates an overflow signal when the counted time value is equal to a predetermined value. A transfer control circuit...
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JPH11163697A |
To perform automatic H/W (hardware) conversion without an MPU processing in the case of processing a change factor at the time of changing the value of a pulse string for comparison during an operation in the case of being composed of a ...
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JPH11136129A |
To provide a PWM conversion circuit suitable for circuit integration. This circuit is provided with a clock generation circuit 21 for generating clock signals CLK, a counter 22 for counting the clock signals CLK, a D/A conversion circuit...
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JP2891711B2 |
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JPH11122938A |
To provide a PWM pulse generation circuit and a control system using the circuit. The magnitude of a count output from an up-down counter 6 and a subtraction result obtained by subtracting a dead time value set to a second register 4 fro...
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JPH11112304A |
To control pulse width and to obtain a pulse signal whose mark rate is special by controlling power voltage through the use of a logic circuit (C-MOS) where the threshold of an input part depends on power voltage. An input signal is appl...
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JP2885256B2 |
A microcomputer having a signal generating circuit which generates pulse width modulation signals defined by a carrier wave, and which controls controlled portions according to pulse width modulating signals. The signal generating circui...
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JP2883059B2 |
To form a pulse which has been subjected to pulse duration modula tion, using a single-integrated circuit by transmitting an address signal with a prescribed timing, based on a signal which has reversely-processed the address of a word r...
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JP2868955B2 |
A pulse generator has a presetting clock synchronous counter having a count enable terminal, the counter which counts up input data using a clock signal whose basic unit of time width corresponds to its one period. The output from said c...
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JPH1169781A |
To miniaturize an electronic apparatus, by a method wherein a pulse- width modulation circuit is constituted of a logic circuit to which a clock signal and a comparator output are inputted and which outputs a logical product result as a ...
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JPH1155335A |
To derive an ASK modulation signal without an error even when a ringing phenomenon is generated when a digital signal is changed from a logical high level to a logical low level. This modulator is provided with a switching diode 1 serial...
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JP2853723B2 |
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JP2853115B2 |
PURPOSE: To provide the weighted unification of signals with simple circuit by charging each capacitance by connecting a power source at a fixed voltage to the capacitance synchronously with an input pulse signal. CONSTITUTION: This sign...
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JP2854352B2 |
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JPH1132222A |
To provide a device which has high data transmitting speed, while maintaining electromagnetic compatibility and in addition, can improve image data used for a high-speed, high image quality system. Image quality of a high image quality p...
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JP2842824B2 |
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JPH114162A |
To provide a clock dividing device which can optionally adjust the dividing ratio, duty and phase and can generate a dividing clock. The count value of a counter 1 is compared with the Hi and Low set values inputted from the terminals 7 ...
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JP2841901B2 |
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