Title:
【発明の名称】クロック信号の高速度のバファリング用の方法及び回路
Document Type and Number:
Japanese Patent JP2003504911
Kind Code:
A
Abstract:
A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancing a voltage follower stage. The steering circuit includes steering transistors positioned between voltage follower transistors and constant current sources. The steering circuit switches all or substantially all of the current from both of the constant current sources through whichever of the two voltage follower transistors is being pulled low, thus doubling the amount of current that is available for slewing when the output is being pulled low. At the same time, since the voltage follower transistor that is being pulled high no longer has to source the constant current I0, the effective maximum current that can be supplied to charge up the load capacitance is increased by approximately I0. The clock buffer provides a higher unity gain bandwidth than a standard CML buffer, while maintaining a well controlled delay which will track other logic gates.
Inventors:
War War, Greg
Application Number:
JP2001508598A
Publication Date:
February 04, 2003
Filing Date:
June 30, 2000
Export Citation:
Assignee:
Vitesse Semiconductor Corporation
International Classes:
H03K19/017; H03K19/0185; H03K19/0948; (IPC1-7): H03K19/0948
Attorney, Agent or Firm:
Takashi Ishida (4 others)