Title:
【発明の名称】キャパシタアレイ
Document Type and Number:
Japanese Patent JP2003504912
Kind Code:
A
Abstract:
A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.
Inventors:
Karsov, Timothy, Buoy
Randell, Barnd, M
Randell, Barnd, M
Application Number:
JP2001508600A
Publication Date:
February 04, 2003
Filing Date:
June 30, 2000
Export Citation:
Assignee:
Bar-Brown Corporation
International Classes:
H01L27/04; H01L21/822; H03M1/06; H03M1/68; H03M1/74; H03M1/46; H03M1/80; (IPC1-7): H03M1/74; H01L21/822; H01L27/04; H03M1/68
Attorney, Agent or Firm:
Akira Asamura (3 outside)