Title:
【発明の名称】高温成長を不要とする低貫通転位密度格子不整合エピ層
Document Type and Number:
Japanese Patent JP2003520444
Kind Code:
A
Abstract:
A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.
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Inventors:
Fitzgerald Eugene A
Application Number:
JP2001553568A
Publication Date:
July 02, 2003
Filing Date:
January 16, 2001
Export Citation:
Assignee:
Amber Wave Systems Corporation
International Classes:
C30B25/02; H01L21/20; H01L21/205; (IPC1-7): H01L21/20; H01L21/205
Attorney, Agent or Firm:
Kenji Yoshida (1 person outside)