Title:
【発明の名称】酸化物がエッチングされないようにした残渣除去方法
Document Type and Number:
Japanese Patent JP2003520446
Kind Code:
A
Abstract:
A method for removing plasma etching-induced residues. In one embodiment, after a portion of photoresist has been used to form a polysilicon gate, the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H20 vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H20 is in the range of from 0.1:1 to 10:1. Next, the present embodiment uses the plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate. Additionally, in the present invention, after the removal of the plasma etching-induced residues, the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured.
Inventors:
Tammy, Zeng
Linda, Riard
Edward, Kay Yeah
Calvin, Todd, Gabriel
Linda, Riard
Edward, Kay Yeah
Calvin, Todd, Gabriel
Application Number:
JP2001553576A
Publication Date:
July 02, 2003
Filing Date:
January 17, 2001
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H01L21/3065; G03F7/42; H01L21/02; H01L21/027; H01L21/3213; (IPC1-7): H01L21/3065; H01L21/027
Attorney, Agent or Firm:
Kenji Yoshitake (4 others)