集積回路アセンブリ - Form Factor, Incorporated

Title:

集積回路アセンブリ

Document Type and Number:

Japanese Patent JP2006510224

Kind Code:

A

Abstract:

In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

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Inventors:

Candros, Igo, Kay
Eldridge, Benjamin, N
Mirror, charles, ray
Spokes, rays, nicholas
Groove, Gary, W
Matthew, Gaetan, El

Application Number:

JP2004560802A

Publication Date:

March 23, 2006

Filing Date:

December 12, 2003

Export Citation:

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Assignee:

Form Factor, Incorporated

International Classes:

H01L25/18; H01L23/13; H01L23/495; H01L23/538; H01L25/04; H01L25/065

Attorney, Agent or Firm:

Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama

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