Title:
ウェル注入を用いた集積回路の改変
Document Type and Number:
Japanese Patent JP2006510225
Kind Code:
A
Abstract:
A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
Inventors:
Butterfly wrap-wai
Clark, William, M., JR.
Bowks, James, Pea.
Harbison, Gavin, Jay.
Clark, William, M., JR.
Bowks, James, Pea.
Harbison, Gavin, Jay.
Application Number:
JP2004560826A
Publication Date:
March 23, 2006
Filing Date:
December 10, 2003
Export Citation:
Assignee:
HRL LABORATORIES, LLC
International Classes:
H01L21/822; H01L21/8234; H01L21/8238; H01L27/02; H01L27/04; H01L27/088; H01L29/76
Domestic Patent References:
| JP2000040809A | 2000-02-08 | |||
| JPH02237038A | 1990-09-19 | |||
| JPS5816565A | 1983-01-31 | |||
| JPH06163539A | 1994-06-10 | |||
| JPH1154606A | 1999-02-26 | |||
| JP2004518273A | 2004-06-17 | |||
| JP2002539636A | 2002-11-19 |
Attorney, Agent or Firm:
Yasuo Ishikawa