Title:
高速DRAMにおける読出しレイテンシを設定及び補償する方法及び装置
Document Type and Number:
Japanese Patent JP2006514760
Kind Code:
A
Abstract:
An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.
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Inventors:
Brent Keith
Brian johnson
Rin Feng
Brian johnson
Rin Feng
Application Number:
JP2004532998A
Publication Date:
May 11, 2006
Filing Date:
August 27, 2003
Export Citation:
Assignee:
MICRON TECHNOLOGY,INC.
International Classes:
G06F12/00; G06F12/06; G11C7/10; G11C11/407; G11C11/4076
Attorney, Agent or Firm:
Kosaku Sugimura
Kazuaki Takami
Hiroshi Tokunaga
Yoshiyuki Iwasa
Shiro Fujitani
Kiyoshi Kuruma
Kazuyuki Tomita
Kazuaki Takami
Hiroshi Tokunaga
Yoshiyuki Iwasa
Shiro Fujitani
Kiyoshi Kuruma
Kazuyuki Tomita