Title:
非メインCPU/OSベースの動作環境
Document Type and Number:
Japanese Patent JP2006515094
Kind Code:
A
Abstract:
An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.
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Inventors:
Carduck, james
Brian, Belmont
Kumar, Musa
Riley jackson
Dunners, Gunner
Foland, richard
Gupta, Vivek
Hackins, jeffrey
Fleming, christopher
Gadam setti, yuma
Brian, Belmont
Kumar, Musa
Riley jackson
Dunners, Gunner
Foland, richard
Gupta, Vivek
Hackins, jeffrey
Fleming, christopher
Gadam setti, yuma
Application Number:
JP2005518466A
Publication Date:
May 18, 2006
Filing Date:
January 12, 2004
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F1/32; G06F1/00; G06F9/06; G06F9/44; G06F13/10; G06F
Domestic Patent References:
| JPH0926832A | 1997-01-28 | |||
| JP2002073497A | 2002-03-12 | |||
| JP2000284858A | 2000-10-13 | |||
| JP2001325203A | 2001-11-22 | |||
| JP2000231533A | 2000-08-22 |
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito