Title:
トランジスタと導線とを備えた半導体集積回路
Document Type and Number:
Japanese Patent JP2006519474
Kind Code:
A
Abstract:
An integrated semiconductor circuit includes a transistor and a strip conductor ( 11 ). The transistor includes a first ( 1 ) and a second source/drain region ( 2 ) and a gate electrode. The strip conductor ( 11 ) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor ( 11 ) extends along a first direction (x) in the area of the transistor. The second source/drain region ( 2 ) is arranged offset with respect to the first source/drain region ( 1 ) in the first direction (x). The transistor thus formed has an inversion channel (K 1 ) that only extends between two corner areas ( 1 a , 2 a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.
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Inventors:
Forlas, Joac
Application Number:
JP2005518515A
Publication Date:
August 24, 2006
Filing Date:
March 01, 2004
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L21/8247; H01L21/336; H01L21/8246; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kenzo Hara International Patent Office