Title:
集積回路メモリーセル及びその製法
Document Type and Number:
Japanese Patent JP2007535132
Kind Code:
A
Abstract:
An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The second source/drain may be included in a digit line inner conductor connecting a digit line to a transistor channel of the vertical transistor. The channel may include a semiconductive upward extension of the combined first electrode and first source/drain. The memory cell may be included in an array of a plurality of such memory cells wherein the second electrode is a common electrode among the plurality. The memory cell may provide a straight-line conductive path between the first electrode and a digit line, the path extending through the vertical transistor.
Inventors:
Patterson, Alexander
Application Number:
JP2006545426A
Publication Date:
November 29, 2007
Filing Date:
December 15, 2004
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L21/8242; H01L27/10; H01L27/108; H01L21/02; H01L27/12
Domestic Patent References:
| JPS62274771A | 1987-11-28 | |||
| JPS6329571A | 1988-02-08 | |||
| JPS6070758A | 1985-04-22 | |||
| JP2001102549A | 2001-04-13 | |||
| JPS6173366A | 1986-04-15 | |||
| JP2003179161A | 2003-06-27 | |||
| JPS61234066A | 1986-10-18 | |||
| JPS5956763A | 1984-04-02 | |||
| JPH06216337A | 1994-08-05 | |||
| JPH05160408A | 1993-06-25 |
Attorney, Agent or Firm:
Nomura Yasuhisa
Takenori Hiroe
Takanobu Takekawa
High Shinichi Ara
Tsutomu Nishio
Takenori Hiroe
Takanobu Takekawa
High Shinichi Ara
Tsutomu Nishio