Title:
高められた過消去耐性制御ゲート方式のメモリ構成
Document Type and Number:
Japanese Patent JP2009502001
Kind Code:
A
Abstract:
The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
Inventors:
Nicole, Telecco
Nguyen, Victor
Nguyen, Victor
Application Number:
JP2008521391A
Publication Date:
January 22, 2009
Filing Date:
June 13, 2006
Export Citation:
Assignee:
ATMEL CORPORATION
International Classes:
G11C16/06; G11C16/04
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa