Title:
同時スイッチングノイズを低減するためのデバイス及び方法
Document Type and Number:
Japanese Patent JP2009502000
Kind Code:
A
Abstract:
By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
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Inventors:
Messiah, jason
Application Number:
JP2008519536A
Publication Date:
January 22, 2009
Filing Date:
June 28, 2006
Export Citation:
Assignee:
TERADYNE INCORPORATED
International Classes:
G11C11/413
Domestic Patent References:
| JPH05334206A | 1993-12-17 | |||
| JPH1049271A | 1998-02-20 | |||
| JPH06161620A | 1994-06-10 | |||
| JP2004133961A | 2004-04-30 | |||
| JPH098671A | 1997-01-10 | |||
| JPH09186607A | 1997-07-15 | |||
| JP2004129258A | 2004-04-22 | |||
| JPS63250000A | 1988-10-17 | |||
| JPH10190751A | 1998-07-21 | |||
| JPH08101813A | 1996-04-16 |
Attorney, Agent or Firm:
Kazuo Shamoto
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko