Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2019161067
Kind Code:
A
Abstract:
To suppress deterioration in electric characteristics.SOLUTION: A semiconductor device comprises: a substrate 10; a laminate 100 provided above the substrate and including a plurality of conductive layers 70 laminated between and via insulation layers 72; a first semiconductor layer 20 extending a lamination direction of the laminate in the laminate; a memory layer 30 provided between the first semiconductor layer and the plurality of conductive layers; and a second semiconductor layer 60 in contact with an upper end part of the first semiconductor layer. The second semiconductor layer comprises a third semiconductor layer 62 containing phosphorous and a fourth semiconductor layer 61 containing carbon and provided between the first semiconductor layer and the third semiconductor layer.SELECTED DRAWING: Figure 2
Inventors:
SATO HIROYASU
Application Number:
JP2018047132A
Publication Date:
September 19, 2019
Filing Date:
March 14, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H01L21/336; H01L27/11524; H01L27/11556; H01L27/1157; H01L27/11582; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken