Title:
MEMORY SYSTEM, ITS CONTROL METHOD, AND PROGRAM
Document Type and Number:
Japanese Patent JP2019168853
Kind Code:
A
Abstract:
To reduce latency without reducing reliability.SOLUTION: A memory system according to an embodiment is provided with a nonvolatile memory for selectively executing any one of a plurality of read operations and a memory controller for instructing a read command for causing the nonvolatile memory to execute any one of the plurality of read operations. The memory controller receives a read request and estimates information on reliability when assuming that the memory has performed the read operation at a physical address where the read request aims. The memory controller selects from the plurality of read operations a read operation for causing, based on the estimated reliability information, the nonvolatile memory to execute first with respect to the read request, and instructs the nonvolatile memory to execute the selected read operation in a first read command first issued to the nonvolatile memory in response to the acceptance of the read request.SELECTED DRAWING: Figure 3
Inventors:
KOJIMA YOSHIHISA
Application Number:
JP2018055169A
Publication Date:
October 03, 2019
Filing Date:
March 22, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
G06F11/10
Attorney, Agent or Firm:
Sakai International Patent Office