Title:
SiC-SOI DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2020013845
Kind Code:
A
Abstract:
To provide an SiC-SOC device realizing high breakdown voltage without thickening an SOI layer, in a wafer adhesive type dielectric isolation structure, and to provide a manufacturing method thereof.SOLUTION: The device region RD of an SiC-SOI device 1001 includes a first trench 8 surrounding an N--type drift region 3A continuously or intermittently, and not penetrating an SiC substrate, an N+-type lateral portion diffusion region 5 formed on both lateral faces of the first trench 8, an N+-type bottom portion diffusion region 4 formed below the N--type drift region 3A in contact with the N+-type lateral portion diffusion region 5, and multiple thin insulation films 23 formed near the surface of the drift region at an interval of 0.4 μm or less. A peripheral region RC includes a second trench 10 formed to surround the first trench 8 continuously and penetrating the SiC substrate, and a separation insulation film region 11 formed on both lateral faces of the second trench 10.SELECTED DRAWING: Figure 3
Inventors:
AKIYAMA HAJIME
YOSHINO MANABU
YOSHINO MANABU
Application Number:
JP2018134022A
Publication Date:
January 23, 2020
Filing Date:
July 17, 2018
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/872; H01L29/06; H01L29/47; H01L29/786
Domestic Patent References:
| JP2008085190A | 2008-04-10 | |||
| JP2008530776A | 2008-08-07 | |||
| JPH11297815A | 1999-10-29 | |||
| JP2005531127A | 2005-10-13 | |||
| JP2016096165A | 2016-05-26 | |||
| JP2010157582A | 2010-07-15 |
Foreign References:
| US20040067625A1 | 2004-04-08 | |||
| US20100033059A1 | 2010-02-11 | |||
| US20170323970A1 | 2017-11-09 | |||
| US20140061731A1 | 2014-03-06 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita