Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2021044035
Kind Code:
A
Abstract:
To perform efficiently and effectively calibration of a memory physical layer circuit of each channel even if the number of reference resistance is reduced.SOLUTION: A memory system comprises: a plurality of non-volatile memories; a controller that includes a plurality of memory physical layer circuits arranged corresponding to a plurality of channels, a pad for calibration corresponding to the plurality of memory physical layer circuits, and a processor which controls the plurality of memory physical layer circuits, and that is connected to the plurality of non-volatile memories via the plurality of channels; and a single reference resistance connected to the plurality of memory physical layer circuits via the pad. The output based on ZQ calibration of the plurality of memory physical layer circuits is wired OR connected, and connected to the single reference resistance via the pad, and the processor performs calibration of each of the plurality of memory physical layer circuits in a time division manner using the single reference resistance.SELECTED DRAWING: Figure 2
Inventors:
KOIZUMI SHINYA
Application Number:
JP2019164335A
Publication Date:
March 18, 2021
Filing Date:
September 10, 2019
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
G11C7/10; G06F12/00; G06F13/16
Attorney, Agent or Firm:
Hidekazu Miyoshi
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu