Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2602219
Kind Code:
B2
Abstract:
A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.
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Inventors:
Kimura Shinichiro
Yoshimoto Kawamoto
Tohru Kaga
Hideo Sakunan
Yoshimoto Kawamoto
Tohru Kaga
Hideo Sakunan
Application Number:
JP2452987A
Publication Date:
April 23, 1997
Filing Date:
February 06, 1987
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L27/10; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP6286853A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)