Title:
【発明の名称】位相情報検出回路
Document Type and Number:
Japanese Patent JP2731151
Kind Code:
B2
Abstract:
A sample rate conversion circuit converts first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency. A ring oscillator has a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop so as to output polyphase delay clock signals and a predetermined self-excited oscillation signal. A phase-locking circuit applies a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of the voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from the ring oscillator. A latch circuit latches the polyphase delay clock signals output from the ring oscillator in accordance with the second clock signal. An interpolation coefficient generator generates an interpolation coefficient corresponding to phase data between the first and second clock signals in accordance with the polyphase delay clock signals latched by the latch circuit. An interpolating circuit interpolates two adjacent data of the first digital data by using the interpolation coefficient generated by the interpolation coefficient generator and outputting the interpolated data as the second digital data.
Inventors:
YAMADA MASAHIRO
KAWAI KYOYUKI
KAWAI KYOYUKI
Application Number:
JP23394787A
Publication Date:
March 25, 1998
Filing Date:
September 18, 1987
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H03L7/06; G01R25/00; H03H17/00; H03H17/06; H04B14/04; H04L7/00; (IPC1-7): H04B14/04; H04L7/00
Domestic Patent References:
| JP62101112A | ||||
| JP57115015A |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)