Title:
【発明の名称】均等化パルス幅制御回路
Document Type and Number:
Japanese Patent JP3321668
Kind Code:
B2
Abstract:
A circuit for controlling an equalization pulse width is disclosed that enables a stable data and minimizes or reduces a speed delay. The control circuit for the equalization pulse width includes a pulse generator for forming a predetermined pulse width in accordance with a set option when address signals are transited, and an addition unit for combining pulses formed by each of the address signals. A pulse latch unit continuously latches an equalization signal in an enabled state when signals are all enabled using a signal by which a redundancy Y-selection signal is enabled when a redundancy occurs in a coding signal from a Y-predecoder.
Inventors:
Sun-Ha Park
Application Number:
JP3166499A
Publication Date:
September 03, 2002
Filing Date:
February 09, 1999
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
G11C11/41; G11C8/18; G11C11/413; G11C29/04; H03K5/00; H03K5/04; H04L7/00; H04L25/04; (IPC1-7): G11C29/00; G11C11/41; G11C11/413
Domestic Patent References:
| JP6203592A | ||||
| JP554690A | ||||
| JP383299A |
Attorney, Agent or Firm:
Fumio Sasashima (1 person outside)