Title:
標本化回路を形成する薄膜回路素子を有する電子装置
Document Type and Number:
Japanese Patent JP3987588
Kind Code:
B2
Abstract:
In an LCD or other electronic device, thin-film circuit elements on a substrate (100) form a sample-and-hold or other sampling circuit (10). The circuit (10) comprises a TFT (Ts) as a sampling transistor and preferably another TFT (T2) to compensate for displacement currents in charging and discharging the insulated gate (121) of the sampling TFT. Even when T2 is included, a slow drift in output voltage (Vo) is observed when Ts switches off, and this limits use of the circuit, especially in large area active-matrix devices. In accordance with the invention this slow drift is removed or significantly reduced by injecting minority carriers into the channel region of Ts (and T2) from a doped opposite-type region (119) or Schottky contact region (119) which is forward biased via a thin-film supply line (129). The minority carriers neutralise majority carriers which are being slowly released by thermal emission from trapping states in the TFT body.
Inventors:
John Richard Alan Aires
Martin John Edwards
Martin John Edwards
Application Number:
JP11284494A
Publication Date:
October 10, 2007
Filing Date:
May 26, 1994
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H01L29/78; H01L29/786; H01L27/12; G02F1/1362
Domestic Patent References:
| JP4317376A | ||||
| JP3055829A | ||||
| JP2113440A | ||||
| JP63223788A | ||||
| JP62065018A | ||||
| JP58170119A |
Attorney, Agent or Firm:
Kosaku Sugimura
Yasunori Sato
Norita Tomita
Umemoto Masao
Takashi Nihei
Yasunori Sato
Norita Tomita
Umemoto Masao
Takashi Nihei