Title:
パワー半導体デバイス内のラテラル素子
Document Type and Number:
Japanese Patent JP4114212
Kind Code:
B2
Abstract:
A method of regulating the gain or sensitivity of a lateral component, formed in the upper surface of a first conductivity type semiconductor wafer (N1), involves subjecting the back face to no doping or to overdoping of first conductivity type, when the gain or sensitivity of the lateral component is to be reduced, and to second conductivity type doping, when the gain or sensitivity of the lateral component is to be increased. Also claimed are (i) a lateral transistor or thyristor formed in the front face of a lightly doped first conductivity type semiconductor, a second conductivity type layer being provided on the back face of the wafer; and (ii) a p-n junction diode assembly formed in the front face of a lightly doped first conductivity type semiconductor wafer, the back face of the substrate including a heavily doped first conductivity type region.
Inventors:
Erik Bernier
Jean-Michel Simone
Jean-Michel Simone
Application Number:
JP2444097A
Publication Date:
July 09, 2008
Filing Date:
January 24, 1997
Export Citation:
Assignee:
STMicroelectronics Society Anonymous
International Classes:
H01L29/78; H01L21/336; H01L21/8234; H01L27/08; H01L27/088; H01L29/735; H01L29/74; H01L29/861
Domestic Patent References:
| JP6069343A | ||||
| JP3155673A |
Attorney, Agent or Firm:
Keiichi Yamamoto