Title:
フラッシュメモリ装置の消去時にバンド間電流および/またはアバランシェ電流を減少させるためのバイアス方法および構造
Document Type and Number:
Japanese Patent JP4197843
Kind Code:
B2
Abstract:
A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.
Inventors:
Sobeck, Daniel
Sir Gate, Timothy James
Runing, Scott Di
Chang, Bay-Han
Hadad, Samya S
Sir Gate, Timothy James
Runing, Scott Di
Chang, Bay-Han
Hadad, Samya S
Application Number:
JP2000539481A
Publication Date:
December 17, 2008
Filing Date:
December 18, 1998
Export Citation:
Assignee:
SPANSION LLC
International Classes:
G11C16/02; G11C16/04; G11C16/14; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP9027560A | ||||
| JP6275842A | ||||
| JP9008153A | ||||
| JP5226665A | ||||
| JP3245566A | ||||
| JP10065029A | ||||
| JP11126494A | ||||
| JP5343700A | ||||
| JP11039890A | ||||
| JP10335504A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa