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Title:
半導体集積回路装置およびその製造方法
Document Type and Number:
Japanese Patent JP4215711
Kind Code:
B2
Abstract:

To ensure the contact area of a contact hole between word lines and a through hole formed in the upper portion of the contact hole in a DRAM whose memory cell size is miniaturized.

The diameter of the upper portion of a plug 14 embedded in the space (contact holes 12 and 13) of a gate electrode 7 (a word line WL) is made greater than the diameter of the bottom by making the upper end height of a side wall insulating film 11 composed of silicon oxide lower than the top surface height of a cap insulating film 9. This makes it possible to fully secure the contact area of holes because the surface area of the contact hole 13 is large, even if the center of a through hole 36 is shifted from that of the contact hole 13 due to photomask misalignment and the like when the through hole 36 is formed in the upper portion of the contact hole 13.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Satoru Yamada
Shizuka Oyu
Tokunaga Naofumi
Hiroyuki Enomoto
Toshihiro Sekiguchi
Application Number:
JP2004367664A
Publication Date:
January 28, 2009
Filing Date:
December 20, 2004
Export Citation:
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Assignee:
Elpida Memory Co., Ltd.
International Classes:
H01L21/8242; H01L27/108
Domestic Patent References:
JP10070191A
JP10214894A
JP11177089A
JP9219517A
JP11074475A
Foreign References:
GB2338596A
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata