Title:
情報再生装置
Document Type and Number:
Japanese Patent JP4232207
Kind Code:
B2
Abstract:
An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.
Inventors:
Hiromi Homma
Application Number:
JP2006351372A
Publication Date:
March 04, 2009
Filing Date:
December 27, 2006
Export Citation:
Assignee:
NEC
International Classes:
G11B20/14; H03L7/06
Domestic Patent References:
| JP2001195830A | ||||
| JP2006024265A | ||||
| JP2006134501A |
Attorney, Agent or Firm:
Kiyoshi Inagaki
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