Title:
統合ディレクトリとプロセッサキャッシュを備えたコンピュータシステム
Document Type and Number:
Japanese Patent JP4237142
Kind Code:
B2
Abstract:
A computer system with an integrated directory and processor cache. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of cache memory subsystem, such as an L2 cache, associated with a processor core. In one particular implementation, directory entries are stored within the cache memory subsystem to provide indications of lines (or blocks) that may be cached in modified, exclusive, or owned coherency states. The absence of a directory entry for a particular line may imply that the line is cached in either shared or invalid states.
Inventors:
Patrick Conway
Application Number:
JP2004540279A
Publication Date:
March 11, 2009
Filing Date:
September 18, 2003
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F12/08
Domestic Patent References:
| JP10260898A | ||||
| JP11232173A | ||||
| JP7121493A | ||||
| JP6309216A |
Foreign References:
| US20020087778 | ||||
| US6763432 | ||||
| US5802600 | ||||
| WO2000038070A1 | ||||
| WO2000038069A1 |
Attorney, Agent or Firm:
Masatake Suzuki
Ryota Sano
Yoshito Muramatsu
Ryota Sano
Yoshito Muramatsu