PURPOSE: To make it possible to estimate the erroneous operation of a product due to a delay time subsequent to the completion of a layout by a method wherein a corrected delay time is converted into data in an input format to a logical simulator and the data is compared with an expected output value at the time of the initial design.

CONSTITUTION: A plurality of representative values of a load capacity are given to a reference gate by a circuit simulator and delay times to correspond to the representative values are calculated. Functions of the load capacity to the delay times are created from the given representative values of the load capacity and the found delay times. On the other hand, the parasitic capacitance of a designed layout pattern to be verified is extracted, a drive gate of each wiring and the extracted parasitic capacitance are applied to the functions of the load capacity to the delay times and a delay time in the reference gate is calculated. A correction of the delay time is conducted, this corrected delay time is converted into data in an input format to a logical simulator and the data is compared with an expected output value at the time of the initial design. Thereby, the erroneous operation of a product due to the delay time subsequent to the completion of a layout can be estimated.