Title:
半導体試験装置および半導体試験方法
Document Type and Number:
Japanese Patent JP4261432
Kind Code:
B2
Abstract:
A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal; and a comparing unit that compares a response signal, which is output from the DUT in response to the input of the test signal, and the reference signal by offsetting the test signal contained in a composite signal of the test signal and the response signal and the test signal contained in the comparison signal. The DUT is determined to be defective or not based on a result of comparison by the comparing unit.
Inventors:
Shoji Kojima
Application Number:
JP2004203278A
Publication Date:
April 30, 2009
Filing Date:
July 09, 2004
Export Citation:
Assignee:
Advantest Corporation
International Classes:
G01R31/28
Domestic Patent References:
| JP2002507754A | ||||
| JP5081753U |
Attorney, Agent or Firm:
Hiroaki Sakai