Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4302952
Kind Code:
B2
Abstract:
An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.
Inventors:
Naruo Sato
Masataka Kase
Masataka Kase
Application Number:
JP2002254672A
Publication Date:
July 29, 2009
Filing Date:
August 30, 2002
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
H01L29/78; H01L21/265; H01L21/28; H01L21/3215; H01L21/336; H01L21/8238; H01L27/092
Domestic Patent References:
| JP7297400A | ||||
| JP9074199A | ||||
| JP8148680A | ||||
| JP3084962A | ||||
| JP2000340790A |
Attorney, Agent or Firm:
Takayoshi Kokubun