Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4400999
Kind Code:
B2
Abstract:
An internal signal RAS generated in accordance with command input and indicating activation of a row is delayed in accordance with a dock signal int.CLKI, and thereby a sense amplifier activating signal is issued. A time from activation of a word line by a signal WLT to activation of a sense amplifier can be longer than that in a normal case so that a minute leak from a bit line can be detected.
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Inventors:
Seiji Sawada
Kiyohiro Furuya
Mikio Asakura
Kiyohiro Furuya
Mikio Asakura
Application Number:
JP2000195971A
Publication Date:
January 20, 2010
Filing Date:
June 29, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G01R31/28; G11C7/10; G11C29/04; G11C7/22; G11C11/401; G11C11/407; G11C29/00; G11C29/50
Domestic Patent References:
| JP2001195900A | ||||
| JP11162195A | ||||
| JP6259998A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai