Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4428531
Kind Code:
B2
Abstract:
An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.
Inventors:
Bruce Allen Boeck
Jeff Thomas Wessel
Terry Grant Sparks
Jeff Thomas Wessel
Terry Grant Sparks
Application Number:
JP2005117776A
Publication Date:
March 10, 2010
Filing Date:
April 15, 2005
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L21/28; H01L21/316; H01L21/768; H01L21/318; H01L23/522; H01L23/532
Domestic Patent References:
| JP7335747A | ||||
| JP7326671A | ||||
| JP64031831A | ||||
| JP7326670A | ||||
| JP2086146A | ||||
| JP63098134A |
Attorney, Agent or Firm:
Atsushi Honda
Miho Ikegami
Miho Ikegami