Title:
デュアル-MACプロセッサおよびデュアル-MACコプロセッサを有するDSP
Document Type and Number:
Japanese Patent JP4477278
Kind Code:
B2
Abstract:
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.
Inventors:
Rhino, Gilbert Sea
Kumar, Hemant
Lee, Way-Shin
Kumar, Hemant
Lee, Way-Shin
Application Number:
JP2001562278A
Publication Date:
June 09, 2010
Filing Date:
February 23, 2001
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F7/00; G06F7/48; G06F7/544; G06F9/302; G06F9/38; G06F15/78; G06F17/10
Domestic Patent References:
| JP6325070A | ||||
| JP9305377A | ||||
| JP11306163A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Toshio Shirane
Sadao Muramatsu
Ryo Hashimoto
Toshio Shirane