Title:
結合された積和演算器を備えたデジタル信号プロセッサ
Document Type and Number:
Japanese Patent JP4477279
Kind Code:
B2
Abstract:
Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
More Like This:
Inventors:
Rhino, Gilbert Sea
Chen, Shufen
Shu, De Dee
Chen, Shufen
Shu, De Dee
Application Number:
JP2001562296A
Publication Date:
June 09, 2010
Filing Date:
February 23, 2001
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F7/00; G06F7/544; G06F17/10
Domestic Patent References:
| JP10063647A |
Foreign References:
| WO1999038088A1 |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Toshio Shirane
Sadao Muramatsu
Ryo Hashimoto
Toshio Shirane