Title:
半導体ウェハを処理する方法およびシステム
Document Type and Number:
Japanese Patent JP4562991
Kind Code:
B2
Abstract:
A method and system for the processing of one or more wafers in a process tool is provided, the method comprising subjecting the one or more wafer in a reaction chamber to a process, generating an inhibit next load flag on predefined conditions, the inhibit next load flag not effecting already started processing of a wafer. Prior to the start of the processing of a wafer, a check is performed to see if an inhibit next load flag has been set. When upon checking it has been found that an inhibit next load has been set, the start of the process in the reaction chamber is prohibited. The method further includes providing pre-programmed recovery procedures, such that after execution of a pre-programmed recovery procedure the to be processed wafer of which the start of the processing is prohibited ends in a defined state such that the tool can be used for further processing.
Inventors:
Cornelius Khanstra
Marinus Jan Van Dar Pol
Yang Zinger
Marinus Jan Van Dar Pol
Yang Zinger
Application Number:
JP2003029767A
Publication Date:
October 13, 2010
Filing Date:
February 06, 2003
Export Citation:
Assignee:
IS M International Namrose Fuennaught Shap
International Classes:
H01L21/02; H01L21/677; H01L21/00
Domestic Patent References:
| JP6104328A |
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Toru Miyamae
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Toru Miyamae