Title:
半導体集積回路及びその半導体集積回路を含んだ半導体システム
Document Type and Number:
Japanese Patent JP4754355
Kind Code:
B2
Abstract:
For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11 . The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11 . The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11 . The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.
Inventors:
Hou Houba
Yoichiro Mae
Hisato Yoshida
Yoichiro Mae
Hisato Yoshida
Application Number:
JP2005517779A
Publication Date:
August 24, 2011
Filing Date:
February 08, 2005
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G01R31/28; G01R31/319; G06F11/22; H01L21/822; H01L27/04
Domestic Patent References:
| JPH07239370A | 1995-09-12 | |||
| JPS60231186A | 1985-11-16 | |||
| JP2001343427A | 2001-12-14 | |||
| JP2004021833A | 2004-01-22 |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Yoneda Keikei
Seki Kei
Yasuya Sugiura
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Yoneda Keikei
Seki Kei
Yasuya Sugiura