Title:
回路装置およびその製造方法
Document Type and Number:
Japanese Patent JP4785139
Kind Code:
B2
Abstract:
Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.
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Inventors:
Yusuke Igarashi
Takasagi Sadamichi
Motoichi Nezu
Takaya Kusobe
Takasagi Sadamichi
Motoichi Nezu
Takaya Kusobe
Application Number:
JP2006510320A
Publication Date:
October 05, 2011
Filing Date:
February 18, 2005
Export Citation:
Assignee:
ON Semiconductor Trading Limited
International Classes:
H01L23/14; H01L23/433; H01L25/16; H05K1/02; H01L21/56; H05K1/05; H05K3/06; H05K3/28
Domestic Patent References:
| JPH0496258A | 1992-03-27 | |||
| JP2001177022A | 2001-06-29 | |||
| JPS63260198A | 1988-10-27 | |||
| JPH0254265U | 1990-04-19 | |||
| JP2001217511A | 2001-08-10 | |||
| JPH09130018A | 1997-05-16 | |||
| JPH01266786A | 1989-10-24 | |||
| JP2001196738A | 2001-07-19 | |||
| JP2002198619A | 2002-07-12 |
Attorney, Agent or Firm:
Takashi Okada
Yoshitaka Okada
Naoko Shiraishi
Yoshitaka Okada
Naoko Shiraishi