Title:
縦形MOSトランジスタ
Document Type and Number:
Japanese Patent JP5008246
Kind Code:
B2
Abstract:
A vertical MOS transistor which is reduced in size and cost and which has high drive performance, reliability and yield is provided. Also provided is a method of manufacturing the vertical MOS transistor. A polycrystalline silicon gate electrode is buried halfway down a trench and an intermediate insulating film is put on top of the gate electrode to fill the rest of the trench. The intermediate insulating film then receives etch-back to form a metal electrode in a self-aligning manner without intervention of a contact hole. This eliminates the need to allow a layout margin for misalignment or the like and therefore makes it possible to reduce a transistor area. This also gives the transistor high reliability since the metal electrode is leveled thoroughly.
Inventors:
Hirofumi Harada
Application Number:
JP2003075344A
Publication Date:
August 22, 2012
Filing Date:
March 19, 2003
Export Citation:
Assignee:
Seiko Instruments Inc.
International Classes:
H01L21/28; H01L29/78; H01L21/336; H01L29/417; H01L29/423; H01L29/49
Domestic Patent References:
| JP11354780A | ||||
| JP2000252468A | ||||
| JP2001210801A |
Attorney, Agent or Firm:
Kentaro Kuhara
Noriaki Uchino
Nobuyuki Kimura
Noriaki Uchino
Nobuyuki Kimura