Title:
縦形MOSトランジスタの製造方法
Document Type and Number:
Japanese Patent JP5008247
Kind Code:
B2
Abstract:
In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main surface of the semiconductor substrate and the gate electrode, and the first insulating film is then etched to form side spacers made of the first insulating film on the wall surfaces of the trench so as to overly the gate electrode. A second insulating film is deposited over a main surface of the semiconductor substrate, the gate electrode, and the first insulating film. The second insulating film is then etched back so as to entirely expose the source region and the body contact region. A source metal electrode is formed over the main surface of the semiconductor substrate so as to cover the source region and body contact region.
Inventors:
Hirofumi Harada
Application Number:
JP2003099926A
Publication Date:
August 22, 2012
Filing Date:
April 03, 2003
Export Citation:
Assignee:
Seiko Instruments Inc.
International Classes:
H01L29/78; H01L21/336; H01L21/8238; H01L27/092; H01L29/423
Domestic Patent References:
| JP11354780A | ||||
| JP2001085685A | ||||
| JP2001210801A |
Attorney, Agent or Firm:
Kentaro Kuhara
Noriaki Uchino
Nobuyuki Kimura
Noriaki Uchino
Nobuyuki Kimura