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Title:
半導体集積回路装置及びクロックスキュー計測方法
Document Type and Number:
Japanese Patent JP5018508
Kind Code:
B2
Abstract:

To provide a semiconductor integrated circuit device for accurately measuring clock skew, and to provide a clock skew measurement method.

The semiconductor integrated circuit device includes a clock input terminal 1 for inputting a clock signal of the inside of LSI 100, a measuring signal input terminal 2 for inputting a clock skew measuring signal for measuring the clock skew, a plurality of pieces of F/F3 for inputting a clock signal and the clock skew measuring signal, and a plurality of measuring signal distribution drivers 7 for distributing the clock skew measuring signal to the plurality of the pieces of F/F3 from the measuring signal input terminal 2. The plurality of the pieces of F/F3 are divided into a plurality of F/F groups 5. All F/F3 in F/F groups 5 are directly connected through a signal line to the same measuring signal distribution driver 7, and the clock skew between the plurality of the pieces of F/F3 is measured from an output signal of the plurality of F/F3.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Kenji Niwa
Application Number:
JP2008014699A
Publication Date:
September 05, 2012
Filing Date:
January 25, 2008
Export Citation:
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Assignee:
NEC
International Classes:
G01R31/28; G06F1/10; H01L21/82; H01L21/822; H01L27/04; H03K5/15
Domestic Patent References:
JP8015380A
JP9269847A
JP2006128635A
Attorney, Agent or Firm:
Ken Ieiri



 
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