Title:
使い捨てスペーサを隆起ソース/ドレイン処理に取り入れた半導体デバイスの製造方法
Document Type and Number:
Japanese Patent JP5048480
Kind Code:
B2
Abstract:
A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is then formed epitaxially. The disposable spacer is then removed to expose the substrate proximal to the gate electrode and a shallow implant, such as a halo or extension implant, is introduced into the exposed substrate proximal the gate electrode. A replacement spacer is formed substantially where the disposable spacer existed a source/drain implant is done to introduce a source/drain impurity distribution into the elevated source drain. The gate electrode may include an overlying silicon nitride capping layer and the first silicon nitride spacer may contact the capping layer to surround the polysilicon gate electrode in silicon nitride.
More Like This:
| JPWO2019162801 | How to operate the display device |
| JP5917842 | Semiconductor device |
| JPS60163457 | MANUFACTURE OF SEMICONDUCTOR DEVICE |
Inventors:
Chen, Jiang
Mora, Lord Earl.
Rosseau, Mark A.
Shiho, Yasuhito
Mora, Lord Earl.
Rosseau, Mark A.
Shiho, Yasuhito
Application Number:
JP2007511381A
Publication Date:
October 17, 2012
Filing Date:
April 13, 2005
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L29/786; H01L21/336; H01L21/265; H01L29/78
Domestic Patent References:
| JP2002043567A | ||||
| JP2000058816A | ||||
| JP2004095639A | ||||
| JP5152321A | ||||
| JP2001284468A |
Attorney, Agent or Firm:
Mamoru Kuwagaki