Title:
半導体装置およびその製造方法と、書込み駆動方法および消去駆動方法ならびに液晶表示装置
Document Type and Number:
Japanese Patent JP5118946
Kind Code:
B2
Abstract:
To provide a method for erasing a nonvolatile TFT memory at low voltage by making it possible to erase it through interband tunneling by controlling a body electric potential.
The semiconductor device includes: a substrate; a semiconductor layer formed on the substrate in an island shape; a source region, a drain region, a channel region, and a body region formed in the semiconductor layer; a body contact region continuously formed in the body region; a charge storage layer formed on the semiconductor layer; and a gate electrode formed on the charge storage layer.
COPYRIGHT: (C)2009,JPO&INPIT
Inventors:
Yoshioka Fumiyoshi
Application Number:
JP2007300797A
Publication Date:
January 16, 2013
Filing Date:
November 20, 2007
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP8172199A | ||||
| JP2006190810A | ||||
| JP11340472A | ||||
| JP2002043447A | ||||
| JP2005317965A |
Attorney, Agent or Firm:
Shintaro Nogawa