To improve the throughput of a network processing apparatus.
There are provided transmission control circuits 10W and 10L, each equipped with an FIFO buffer 11 which temporarily stores an IP packet to be transmitted to a communication network, such as, WAN and LAN, packet data generated by a CPU 1 are processed, according to a high-speed clock signal OCK (for example, 130 MHz) which is faster than a standard clock signal RCK (for example, 125 MHz), corresponding to the communication speed of the communications network, and written to an FIFO buffer 11; and the IP packet stored in the FIFO buffer 11 is read out and output to the communications network, according to the standard clock signal RCK. Processing speeds of RGMII circuits 3W and 3L can be set to speeds faster than the standard clock signal RCK, and the throughput of the network processor can be improved.
COPYRIGHT: (C)2009,JPO&INPIT
Takuya Masuko
Tetsuo Makise
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| JP61283258A |
Aniya Setsuo
Toru Yui
Hitoshi Kiyono
Fukuoka Masahiro
Satoshi Shimizu