Title:
キャッシュメモリおよびその制御方法
Document Type and Number:
Japanese Patent JP5622155
Kind Code:
B2
Abstract:
A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected to the cache memory, the tag address constituted by a first sub-tag address and a second sub-tag address. The cache memory classifies the data, according to the time at which a read request has been made, into at least a first generation which corresponds to a read request made at a recent time and a second generation which corresponds to a read request made at a time which is different from the recent time. The first sub-tag address is managed by the CAM. The second sub-tag address is managed by the SRAM. The cache memory allows a plurality of second sub-tag addresses to be associated with a same first sub-tag address.
Inventors:
岡部 翔
阿部 公輝
阿部 公輝
Application Number:
JP2011537244A
Publication Date:
November 12, 2014
Filing Date:
October 19, 2010
Export Citation:
Assignee:
国立大学法人電気通信大学
International Classes:
G06F12/08; G06F12/12
Domestic Patent References:
| JPH06131265A | 1994-05-13 | |||
| JPH0535599A | 1993-02-12 | |||
| JPH08263370A | 1996-10-11 | |||
| JPS62293596A | 1987-12-21 | |||
| JP2003519835A | 2003-06-24 | |||
| JP3850669B2 | 2006-11-29 | |||
| JPH06131265A | 1994-05-13 | |||
| JPH0535599A | 1993-02-12 | |||
| JPH08263370A | 1996-10-11 | |||
| JPS62293596A | 1987-12-21 | |||
| JP2003519835A | 2003-06-24 | |||
| JP3850669B2 | 2006-11-29 |
Attorney, Agent or Firm:
Yoshio Inemoto
Nishikawa 孝
Nishikawa 孝