半導体装置、電界効果トランジスタおよび電子装置

Japanese Patent JP5647986

B2

Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

岡本 康宏
大田 一樹
井上 隆
宮本 広信
中山 達峰
安藤 裕二

JP2011532927A

January 07, 2015

June 16, 2010

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ルネサスエレクトロニクス株式会社

H01L29/78; H01L29/12

JP2001320042A	2001-11-16
JP2003163354A	2003-06-06
JP2004260140A	2004-09-16

WO2008023737A1	2008-02-28
WO2004061971A1	2004-07-22

Shinji Hayami
Amagi 聡

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