Title:
半導体装置及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6455109
Kind Code:
B2
Abstract:
A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.
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Inventors:
Takeyoshi Nishimura
Application Number:
JP2014245948A
Publication Date:
January 23, 2019
Filing Date:
December 04, 2014
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L21/3205; H01L21/60; H01L21/768; H01L23/522
Domestic Patent References:
| JP2000058820A | ||||
| JP2039535A | ||||
| JP61208231A | ||||
| JP2009088381A | ||||
| JP50028271A | ||||
| JP2000021885A | ||||
| JP2004014599A | ||||
| JP2013110373A |
Attorney, Agent or Firm:
Suzuki Isobe