Document Type and Number:
Japanese Patent JPH056354
Kind Code:
B2
Abstract:
The vertical type MOS transistor includes a transistor body region which consists of an N+ type (high concentration N type) substrate having a drain electrode connected on its bottom surface, and an N- type (low concentration N type) layer epitaxially grown on the top surface of the substrate, and a plurality of P type well regions formed with a prescribed interval on the top surface of the N- type layer. Within a P type well region, there are provided N+ type source regions, and an oxidized gate region and a gate electrode that bestride over both of an N+ source region and the N- type drain region which is to function as the effective drain region. There are provided stopper grooves of dug-out form, situated between and at equal distances from the adjacent P type well regions, extending downward from the surface of the N- type drain region parallel to the sides of the P type well regions.
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Inventors:
MIHARA TERUYOSHI
Application Number:
JP10554483A
Publication Date:
January 26, 1993
Filing Date:
June 13, 1983
Export Citation:
Assignee:
NISSAN MOTOR
International Classes:
H01L21/336; H01L29/423; H01L29/78
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