Title:
【発明の名称】スイツチング回路
Document Type and Number:
Japanese Patent JPH07107973
Kind Code:
B2
Abstract:
A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q1, Q2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q2. The threshold voltage of an NMOSFET M2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M3 in the absence of the substrate effect, and the channel conductance WN/LN of the NMOSFET M3 is so set that the threshold voltage VLT1 of the CMOS inverter and the practical threshold voltage VLT2 of the NMOSFET M3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.
Inventors:
Urakami Ken
Suzuki Shiro
Masahiro Iwamura
Ikuro Masuda
Suzuki Shiro
Masahiro Iwamura
Ikuro Masuda
Application Number:
JP5603384A
Publication Date:
November 15, 1995
Filing Date:
March 26, 1984
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H03K19/08; H03K17/04; H03K17/0412; H03K17/567; H03K17/60; H03K17/687; H03K19/017; H03K19/0944; (IPC1-7): H03K17/567; H03K17/04; H03K19/08
Domestic Patent References:
| JP5911034A |
Attorney, Agent or Firm:
Tokuwaka Mitsumasa
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