Document Type and Number:
Japanese Patent JPS5184534
Kind Code:
A
Abstract:
Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.
More Like This:
| WO/2008/152724 | SEMICONDUCTOR STORAGE DEVICE |
| JPS55108993 | MEMORY DEVICE |
| JP2007509490 | 6-transistor FINFET CMOS static RAM cell with increased cell ratio |
Inventors:
HARUKU OO ASUKIN
EDOWAADO SHII JEIKOBUSON
JEEMUZU EMU RII
JOOJI SONODA
EDOWAADO SHII JEIKOBUSON
JEEMUZU EMU RII
JOOJI SONODA
Application Number:
JP14753475A
Publication Date:
July 23, 1976
Filing Date:
December 12, 1975
Export Citation:
Assignee:
IBM
International Classes:
G11C11/412; (IPC1-7): G11C11/34